The expansion connectors can accommodate special-purpose circuits and systems for years to come, so the board can remain at the core of an engineering educational program indefinitely see below for a current list of available expansion boards. We recommend using EDK Version 9. The V2Pro is a mature product. Future Xilinx EDK versions will not. It also provides various recommendations and requirements for usage of the board, including electrical requirements, logic analyzer requirements, and signal integrity issues.
Simulation results using IBIS also are included. Figure shows a simplified block diagram of the ML memory interfaces. This chapter provides functional descriptions of the major blocks within the ML board design. Figure shows a block diagram of the ML board. Refer to the following section for additional information on the major blocks.
This device is packaged in a pin BGA package with a -6 speed grade. This DIMM module has a bit wide data interface. The board also has provisions to interface to a bit wide DIMM. They are packaged in pin TSOP packages. Two SMA connectors are provided for the input of an off-board differential clock. They can be used to hook up to a logic analyzer. All signals from the FPGA to the connectors are matched closely. The even-numbered pins on each header are connected to ground. These switches can be used to externally pull up or pull down any signal on the FPGA.
The red displays are active Low. The decimal points are not connected. The LEDs are active Low. The ML board contains four momentary push buttons. Their functions are as follows:.
These can be depopulated when needed for test purposes. The ML board uses a 5V input voltage source to generate all the on-board voltages 1. The input voltage is specified at 5 V 6. The recommended power supply is a CUI Inc. The slide switch is a CW Industries G This power input has alternate input solder pads.
This regulator provides 2. The PROM operates with a 3. Table lists the operating voltages, maximum currents, and power consumption used by the ML board devices. These results are derived using the Xilinx Power Estimator tool. Chapter 4: Signal Integrity Recommendations and Simulations. The recommendations for the transmission line lengths are as follows:. The 2. The trace lengths on all five DDR components are: 2. For the address and control signals, no termination is required at the FPGA.
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